In a memory such as a static random access memory (SRAM), the pre-charging of the internal nodes of the sense amplifier and bit-lines is started only after the successful read operation and subsequent proper latching of the read data, as controlled by conventional tracking schemes and margins. The pre-charge signals are generated in a global control block, with the pre-charge signal running the width of the memory. As the width or number of bits of the memory increases the RC (Resistive-Capacitive) delay for the set of bit-lines in the last column eventually dominates the cycle time of the memory.